AN3203 datasheet(6/49 Pages) STMICROELECTRONICS

6 / 49 page

Main characteristics and circuit description

AN3203

6/49

Doc ID 17402 Rev 2

and protection needed by the AHB stage and an interface for the PFC controller. The L6591

includes two gate drivers for the half bridge MOSFETs and a fixed frequency

complementary PWM logic with 50 % maximum duty cycle with programmable dead time

and current mode control technique.

Other features of this IC are pulse-by-pulse overcurrent protection, transformer saturation

detection, overload protection (latched or auto-restart), and programmable soft-start. There

is also a high voltage startup circuit, a burst mode logic for low load operation, and the

adaptive UVLO onboard, which are not used in this design as they are designed for adapter

applications (see AN2852).

The following is a description of the power circuit of this stage. The half bridge switches

Q101 and Q102 are connected to the output voltage of the PFC. The half bridge node drives

the series of C101 (DC blocking capacitor) and the primary side of the transformer T1. This

transformer has two secondary windings with a center tap connected to the secondary

ground. The other ends are connected to the sources of MOSFETs Q201 and Q202, which

replace output diodes in order to perform the synchronous rectification. Two extra windings

allow, with few external passive components, a self driven synchronous rectification to be

obtained. This solution allows efficiency to be increased without the extra cost of a

dedicated SR controller IC.

Q201 and Q202 drains are connected to the output inductor L201 that, together with output

capacitors C201 and C202, acts as a low pass filter. The signal +12 VA is then post filtered

(with L5 and C207) to obtain the +12 V output voltage.

The design of transformer T1 is a trade-off between ZVS operation and the required

electrical performance/efficiency. ZVS can be obtained acting on the magnetizing

inductance or on the primary side leakage inductance. In more detail, ZVS could be met by:

●

Decreasing the magnetizing inductance

●

Increasing the leakage inductance

Low values of magnetizing inductance generate high magnetizing current. This helps to

reach ZVS but it also increases the total primary side rms current and therefore the related

losses. In this design a value of 500 µH has been selected.

On the other hand, ZVS could be obtained by increasing the leakage inductance. If such a

parameter is increased, the primary side current takes more time before reversing its

direction and therefore ZVS is more easily met. A high leakage inductance value leads to

duty cycle losses, reducing the effective range of duty cycle usable. This creates problems

with hold-up requirements and makes it necessary to work with very narrow duty cycles with

nominal input voltage generating high rms currents in the circuit.

A value of 12 µH has been selected as the leakage inductance.

Because of these reasons, in this design ZVS is always met at low side MOSFET turn-on

while it is met only for medium-high loads at high side MOSFET turn-on. Even at medium-

low loads Q101 is turned on with a Vds well below the half bridge input voltage.

The L6591 LINE pin is used for startup sequencing. It shares with the L6563S the voltage

divider made up of R20, R21, R22, R29, and R26 that senses the PFC output voltage. The

AHB stage is activated when the bulk voltage reaches about 380 V.

The DISABLE pin (latched protection) is driven by the L6563S PWM_LATCH pin and stops

the AHB stage in case of PFC feedback disconnection.

The oscillator is programmed in order to have a switching frequency of about 80 KHz and to

use the minimum dead time (about 310 ns).

AN3203 数据表(PDF) 6 Page - STMicroelectronics

AN3203 数据表(HTML) 6 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

数据表下载