AN4121

Circuit description

Doc ID 023243 Rev 1

7/26

Figure 4.

Daughterboard circuit schematic

2.2.4

Jumper settings

The onboard jumpers JP1 to JP4 allow the setting of the STPMS2 device according to

Table 2, Table 3, Table 4 and Table 5 below.

AM12799v1

Table 2.

Precision mode and input amplifier gain selection

JP1

MS0

Description

1

GND

LPR, amplifier GAIN selection g3 = 32

1.

Default value.

CLK

LPR, amplifier GAIN selection g0 = 4

3

NCLK

HPR, amplifier GAIN selection g0 = 4

4

VDD

HPR, amplifier GAIN selection g3 = 32