UPD30500 datasheet(8/36 Pages) NEC

8 / 36 page

µPD30500, 30500A, 30500B

Data Sheet U12031EJ4V0DS00

PIN NAMES

BigEndian:

Endian Mode Select

ColdReset:

Cold Reset

ExtRqst:

External Request

GND:

Ground

GNDP:

Quiet GND for PLL

Int (0:5):

Interrupt Request

ModeClock:

Boot Mode Clock

Modeln:

Boot Mode Data In

NC:

No Connection

NMI:

Non-maskable Interrupt Request

RdRdy:

Read Ready

Release:

Release Interface

Reset:

Reset

ScCLR:

Secondary Cache Block Clear

ScCWE (0:1):

Secondary Cache Write Enable

ScDCE (0:1):

Data RAM Chip Enable

ScDOE:

Data RAM Output Enable

ScLine (0:15):

Secondary Cache Line Index

ScMatch:

Secondary Cache Tag Match

ScTCE:

Secondary Cache Tag RAM Chip Enable

ScTDE:

Secondary Cache Tag RAM Data Enable

ScTOE:

Secondary Cache Tag RAM Output Enable

ScValid:

Secondary Cache Valid

ScWord (0:1):

Secondary Cache Word Index

SysAD (0:63):

System Address/Data Bus

SysADC (0:7):

System Address/Data Check Bus

SysClock:

System Clock

SysCmd (0:8):

System Command/Data Identifier

SysCmdP:

System Command/Data Identifier Bus Parity

Validln:

Valid Input

ValidOut:

Valid Output

VDD:

Power Supply (

µPD30500)

VDD:

Power Supply for Processor Core (

µPD30500A, 30500B)

VDDIO:

Power Supply for Processor I/O (

µPD30500A, 30500B only)

VDDOk:

VDD is OK

VDDP:

Quiet VDD for PLL

WrRdy:

Write Ready

UPD30500 数据表(PDF) 8 Page - NEC

UPD30500 数据表(HTML) 8 Page - NEC

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