©

1997,1999

DATA SHEET

©

1997

MIPS Technologies Inc.

MOS INTEGRATED CIRCUIT

Document No. U12031EJ4V0DS00 (4th edition)

Date Published May 2000 N CP(K)

Printed in Japan

DESCRIPTION

The

bit RISC (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed by

Therefore, present

applications can be used as they are.

Note

Under development

Detailed functions are described in the following manual. Be sure to read the manual when

designing your system.

FEATURES

•

Employs 64-bit MIPS-based RISC architecture

•

High-speed processing

•

2-way super scalar 5-stage pipeline

•

5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (

µPD30500)

6.6 SPECint95, 6.6 SPECfp95, 353 MIPS (

µPD30500A)

8 SPECint95, 8 SPECfp95, 423 MIPS (

µPD30500B)

•

High-speed translation buffer mechanism (TLB) (48 entries)

•

Address space

Physical: 36 bits, Virtual: 40 bits

•

Floating-point unit (FPU)

•

Sum-of-products operation instruction supported

•

Primary cache memory (instruction/data: 32 Kbytes each)

•

Secondary cache controller

•

Maximum operating frequency Internal: 200 MHz (

µPD30500), 250 MHz (µPD30500A), 300 MHz (µPD30500B)

External: 100 MHz

•

Selectable external/internal multiple rate from twice to eight times

•

•

Supply voltage: 3.3 V

±5% (

µPD30500)

Core: 2.5 V

±5%, I/O: 3.3 V ±5% (

µPD30500A)

Core: 1.8 V

±0.1 V, I/O: 3.3 V ±5% (

µPD30500B)

µPD30500) is treated as the representative model throughout this

document.

64-BIT MICROPROCESSOR

The mark

shows major revised points.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.