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UPD30500 数据表(PDF) 2 Page - NEC

部件名 UPD30500
功能描述  VR5000TM, VR5000ATM, VR5000BTM 64-BIT MICROPROCESSOR
PDF  36 Pages
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制造商  NEC [NEC]
网页  http://www.nec.com/
标志 NEC - NEC

UPD30500 数据表(HTML) 2 Page - NEC

  UPD30500 Datasheet HTML 1Page - NEC UPD30500 Datasheet HTML 2Page - NEC UPD30500 Datasheet HTML 3Page - NEC UPD30500 Datasheet HTML 4Page - NEC UPD30500 Datasheet HTML 5Page - NEC UPD30500 Datasheet HTML 6Page - NEC UPD30500 Datasheet HTML 7Page - NEC UPD30500 Datasheet HTML 8Page - NEC UPD30500 Datasheet HTML 9Page - NEC Next Button
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µPD30500, 30500A, 30500B
2
Data Sheet U12031EJ4V0DS00
APPLICATIONS
•
High-performance embedded systems
•
Multimedia systems
•
Entry-class computers
•
Image processing systems
ORDERING INFORMATION
Part number
Package
Maximum operating frequency (MHz)
µPD30500RJ-150
223-pin ceramic PGA (48
× 48)
150
µPD30500RJ-180
223-pin ceramic PGA (48
× 48)
180
µPD30500RJ-200
223-pin ceramic PGA (48
× 48)
200
µPD30500S2-150
272-pin plastic BGA (C/D advanced type) (29
× 29)
150
µPD30500S2-180
272-pin plastic BGA (C/D advanced type) (29
× 29)
180
µPD30500S2-200
272-pin plastic BGA (C/D advanced type) (29
× 29)
200
µPD30500AS2-250
272-pin plastic BGA (C/D advanced type) (29
× 29)
250
µPD30500BS2-300Note
272-pin plastic BGA (C/D advanced type) (29
× 29)
300
Note
Under development
MAIN DIFFERENCES BETWEEN VR5000, VR5000A, AND VR5000B
Parameter
VR5000
VR5000A
VR5000BNote 1
Maximum internal operating frequency
150/180/200 MHz
250 MHz
300 MHz
Internal multiplication ratio for clock
2, 3, 4, 5, 6, 7, 8
2, 2.5Note 2, 3, 4, 5, 6, 7, 8
interface input
Supply voltage
3.3 V
±5%
Core: 2.5 V
±5%
Core: 1.8 V
±0.1 V
I/O: 3.3 V
±5%
I/O: 3.3 V
±5%
Package
• 223-pin ceramic PGA
• 272-pin plastic BGA (C/D advanced type)
• 272-pin plastic BGA
(C/D advanced type)
Notes 1. Under development
2. Selectable only when SysClock = 100 MHz



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