AN3387

PM8803 layout guideline

Doc ID 018735 Rev 1

3/12

Table 1.

PM8803 pin descriptions

Pin# Name

Type

Function

1

CTL

Signal to RTN

Input of the pulse width modulator.

CTL pull-up to VB is provided by an external resistor which may be used to bias an

optocoupler transistor.

2VB

Power to RTN

5 V, up to 10 mA bias rail.

This reference voltage can be used to bias an optocoupler transistor.

3

CS

Signal to RTN

Current sense input for current mode control and overcurrent protection.

Current sensing is accomplished using a dedicated current sense comparator. If the

CS pin voltage exceeds 0.5 V the GAT1 pin switches low for cycle-by-cycle current

limiting. CS is internally held low for 60 ns after GAT1 switches high to blank leading

edge current spikes.

4

RTN1

Ground RTN

Power ground for the GAT1 driver.

This pin must be connected to RTN2 and ARTN.

5GAT1

Power to RTN

Main gate driver output of the PWM controller.

DC-DC converter gate driver output with 1 A peak sink-source current capability. (5

Ω typ. MOSFETs).

6VC

Power to RTN

Output of the internal high voltage regulator.

When the auxiliary transformer winding (if used) raises the voltage on this pin above

the 8 V typ. regulation set point, the internal regulator shuts down, reducing the

internal power dissipation. Filter this pin with a 1 µF typ. connected to ground.

7GAT2

Power to RTN

Secondary gate driver output.

AUX gate driver output for active clamp or synchronous rectification designs. 1 A

peak sink-source current capability (5

Ω typ. MOSFETs).

8

ARTN

Ground RTN

Analog PWM supply ground.

RTN for sensitive analog circuitry including the SMPS current limit amplifier.

9

RTN2

Ground RTN

Power ground for the secondary gate driver.

This pin is also connected to the drain of the internal current limiting Power

MOSFET which closes VSS to the return path of the DC-DC converter.

This pin must be connected to RTN1 and ARTN.

10

VSS

Ground VSS

System low potential input.

Diode “OR'd” to the RJ45 connector and PSE’s -48 V supply, it is the more negative

input potential.

11

VDD

Power to VSS

System high potential input.

The diode “OR” of several lines entering the PD, it is the most positive input poten-

tial.

12

VDD

Power to VSS

System high potential input.

The diode “OR” of several lines entering the PD, it is the most positive input poten-

tial.

13

DET

Signal to VSS

Detection resistor pin.

Connect the signature resistance between the DET pin and VDD. Current flows

through the resistor only during the detection phase.

This pin is 100 V rated with negligible resistance with respect to the external 24.9

k

Ω.