PM8803 layout guideline

AN3387

4/12

Doc ID 018735 Rev 1

14

SP

Signal to VSS

Front auxiliary startup pin.

Pulling up this pin to the auxiliary source changes the internal UVLO settings and

allows PD to be powered with voltage lower than nominal PoE voltages. Default

inrush and DC current protection are active. Use a resistor voltage divider from the

auxiliary voltage to VSS to connect this low voltage rating pin. Connect this pin to

VSS if not used.

15

CLS

Signal to VSS

Classification resistor pin.

Connect the classification programming resistor from this pin to VSS.

16

DCCL

Signal to VSS

DC current limit.

A resistor between this pin and VSS sets the current limit for the interface section of

PM8803. It can be set to exceed the IEEE802.3at current limit. Leave the pin open

for standard IEEE 802.3at applications.

17

SA

Signal to RTN

Rear auxiliary startup pin.

Pulling up this pin gives high priority to an auxiliary power source like an external

wall adapter. Use a resistor voltage divider from the auxiliary voltage to ARTN to

connect this low voltage rating pin.

Connect this pin to ARTN if not used.

18

DT

Signal to RTN

Delay time set.

A resistor connected from this pin to ARTN sets the delay time between GAT1 and

GAT2. This pin cannot be left open.

19

FRS

Signal to RTN

Switching frequency set.

An external resistor connected from FRS to ARTN sets the oscillator frequency.

20

T2P

Signal to RTN

Successful 2-event classification indicator.

T2P open drain signal assertion happens when powered by a PSE performing a 2-

events classification.

The T2P is an active low signal.

EP

Ground VSS

Exposed pad.

Connect this to a PCB copper plane to improve heat dissipation; must be electrically

connected to VSS.

Table 1.

PM8803 pin descriptions (continued)

Pin# Name

Type

Function