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AN3393 数据表(PDF) 90 Page - STMicroelectronics |
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AN3393 数据表(HTML) 90 Page - STMicroelectronics |
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90 / 103 page  First-in first-out (FIFO) buffer AN3393 90/103 DocID018750 Rev 4 Figure 28. FIFO_EN connection block diagram 10.2.2 FIFO control register (2Eh) This register is dedicated to FIFO mode selection and watermark configuration. The FMODE[2:0] bits define the selection of the FIFO buffer behavior. Table 97. FIFO enable bit in CTRL_REG6 b7 b6 b5 b4 b3 b2 b1 b0 X FIFO_EN WTM_EN ADD_INC X X X X Table 98. FIFO_CTRL b7 b6 b5 b4 b3 b2 b1 b0 FMODE2 FMODE1 FMODE0 WTMP4 WTMP3 WTMP2 WTMP1 WTMP0 Table 99. FIFO buffer behavior selection FMODE2 FMODE1 FMODE0 FIFO buffer behavior 0 0 0 Bypass mode 0 0 1 FIFO mode 0 1 0 Stream mode 0 1 1 Stream-to-FIFO mode 1 0 0 Bypass-to-Stream mode 1 0 1 Not used 1 1 0 Not used 1 1 1 Bypass-to-FIFO mode |
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