AN3393 datasheet(23/103 Pages) STMICROELECTRONICS

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AN3393

103

The value of the long counter is expressed in two’s complement.

This value is decreased whenever the DEC opcode is executed in the state machine and

the counter value is higher or equal to zero (see Section 6.2.12).

To stop counting, the value -01h must be written in these registers.

When the long counter is full (00h), the LONG bit is set to 1 in the STAT register (18h). The

following state for the long counter is -01h (counter stopped).

Reading of the LC registers resets the LONG bit in the STAT register (18h) to the default

value (0).

4.9

STAT (18h)

Table 14. Status of long counter MSB (17h)

Bit

Name

LC_H_7

LC_H_6

LC_H_5

LC_H_4

LC_H_3

LC_H_2

LC_H_1

LC_H_0

Default

00000000

Table 15. Status of long counter values

LC values

Condition

= -01h

Not valid value, counting stopped

= 00h

Counter full, interrupt occurs and counter set to -01h

> 00h

Counting

Table 16. STAT register

Bit

Name

LONG

SYNCW

SYNC1

SYNC2

INT_SM1 INT_SM2

DOR

DRDY

Default

00000000

Table 17. STAT register description

Bit name

Description

LONG

0= no interrupt, 1= longcounter interrupt flag.

Common to both state machines.

LONG flag is reset to default value by reading the LC registers (16h and 17h).

SYNCW

Common information for OUTW. Waiting on action from host.

0 = no action waiting from host.

1 = host action is waiting after OUTW command.

This bit is reset to 0 whenever OUTS1/OUTS2 is read.

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