AN4116 datasheet(7/38 Pages) STMICROELECTRONICS

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AN4116

Adapter features

Doc ID 023220 Rev 1

7/38

Adapter features

The electrical specifications of the demonstration board are listed below in

Table 1.

Circuit description

The power supply is set in flyback topology. The schematic is given in

Figure 2 and the bill of

materials in

Table 2. The input section includes a resistor R0 for inrush current limiting and a

diode bridge (D0) and Pi filter for EMC suppression (Cin1, Lin, Cin2). The transformer core

is a standard E13. The output voltage value is set in a simple way through the RfbH-RfbL

voltage divider between the output terminal and the FB pin, according to the following

formula:

Equation 1

In fact, the FB pin is the input of an error amplifier and is an accurate 3.3 V voltage

reference. In the schematic the upper resistor RfbH has been split into RfbH1 and RfbH2;

and the lower resistor RfbL into RfbL1 and RfbL2 in order to allow a better tuning of the

output voltage value. The compensation network is connected between the COMP pin

(which is the output of the error amplifier) and the GND pin and is made up of Cp, Cc and

Rc. The resistor RLIM, placed between the LIM and GND pins, has the purpose of reducing

the drain current limitation, from IDLIM to about 250 mA in order to limit the deliverable

output power of the converter and keep the power components safe. At power-up, as the

rectified input voltage rises over the VDRAINSTART threshold, the high voltage current

generator starts charging the VDD capacitor, CVDD, from 0 V up to VDDON. At this point the

Power MOSFET starts switching, the HV current generator is turned off and the IC is biased

by the energy stored in CVDD. In this demonstration board, if jumper J1 is not selected, the

IC is biased through the internal high voltage startup current generator, which is

automatically turned on as the VDD voltage drops to VDDCS_ON and switched off as VDD is

charged up to VDDON (self-biasing). The use of self-biasing means higher power dissipation

and must be avoided if low standby consumption is required. Self-biasing is excluded by

keeping the VDD pin voltage always above the VDDCS_ON threshold. In this board, since the

output voltage is higher than VDDCS_ON, this is obtained selecting jumper J1, which

Table 1.

Electrical specifications

Parameter

Symbol

Value

Input voltage range

VIN

[90 VAC; 265 VAC]

Output voltage

VOUT

12 V

Max. output current

IOUT

0.35 A

Precision of output regulation

ΔV

OUT_HF

± 5%

High frequency output voltage ripple

ΔV

OUT_HF

50 mV

Max. ambient operating temperature

TAMB

60 ºC

⎟⎟⎠

⎞

⎜⎜⎝

⎛

⋅

RfbL

RfbH

OUT

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