AN4116 datasheet(4/38 Pages) STMICROELECTRONICS

4 / 38 page

List of figures

AN4116

4/38

Doc ID 023220 Rev 1

List of figures

Figure 1.

Demonstration board image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3.

VDD waveforms IC externally biased (J1 selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4.

VDD waveforms IC self-biased (J1 not selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5.

Transformer size and pin diagram pin distances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6.

Transformer electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7.

Transformer side view 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8.

Transformer side view 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 9.

Drain current/voltage @ 115 VAC max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10.

Drain current/voltage @ 230 VAC max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11.

Drain current/voltage @ 90 VAC max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 12.

Drain current/voltage @ 265 VAC max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 13.

Line regulation at different loads; IC externally biased (J1 selected) . . . . . . . . . . . . . . . . . 14

Figure 14.

Line regulation at different loads; IC self-biased (J1 not selected) . . . . . . . . . . . . . . . . . . . 14

Figure 15.

Load regulation at different input voltages; IC externally biased (J1 selected). . . . . . . . . . 15

Figure 16.

Load regulation at different input voltages; IC self-biased (J1 not selected) . . . . . . . . . . . 15

Figure 17.

Output voltage ripple @ 115 VAC no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 18.

Output voltage ripple @ 230 VAC no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 19.

Output voltage ripple @ 115 VAC 25 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 20.

Output voltage ripple @ 230 VAC 25 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 21.

Active mode efficiency of the demonstration board

and comparison with energy efficiency standards (IC externally biased) . . . . . . . . . . . . . 17

Figure 22.

PIN vs. VIN at no load and light load; IC externally biased (J1 selected) . . . . . . . . . . . . . . 19

Figure 23.

PIN vs. VIN at no load and light load, IC self-biased (J1 not selected) . . . . . . . . . . . . . . . . 19

Figure 24.

Efficiency @ PIN=1 W; IC externally biased (J1 selected) . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 25.

Efficiency @ PIN=1 W; IC self-biased (J1 not selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 26.

PIN @ POUT = 250 mW; IC externally biased (J1 selected) . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 27.

PIN @ POUT = 250 mW; IC self-biased (J1 not selected) . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 28.

Soft-start at startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 29.

Soft-start at startup (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 30.

Output short-circuit applied: OLP tripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 31.

Output short-circuit maintained: OLP steady-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 32.

Output short-circuit maintained: OLP steady-state (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 33.

Output short-circuit removal and converter restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 34.

Feedback loop failure protection: tripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 35.

Feedback loop failure protection: steady-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 36.

Feedback loop failure protection: steady-state, zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 37.

Feedback loop failure protection: converter restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 38.

Control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 39.

Thermal map at VIN=85 VAC, TAMB=25 °C, full load; IC externally biased . . . . . . . . . . . . . 27

Figure 40.

Thermal map at VIN=85 VAC, TAMB=25 °C, full load; IC self-biased . . . . . . . . . . . . . . . . . . 27

Figure 41.

Thermal map at VIN=115 VAC, full load, TAMB=25 °C; IC externally biased. . . . . . . . . . . . 27

Figure 42.

Thermal map at VIN=115 VAC, full load, TAMB=25 °C; IC self-biased . . . . . . . . . . . . . . . . . 27

Figure 43.

Thermal map @ VIN=230 VAC, full load, TAMB=25 °C; IC externally biased. . . . . . . . . . . . 28

Figure 44.

Thermal map @ VIN=230 VAC, full load, TAMB=25 °C; IC self-biased . . . . . . . . . . . . . . . . 28

Figure 45.

Thermal map @ VIN=265 VAC, full load, TAMB=25 °C; IC externally biased. . . . . . . . . . . . 28

Figure 46.

Thermal map @ VIN=265 VAC, full load, TAMB=25 °C; IC self-biased . . . . . . . . . . . . . . . . 28

Figure 47.

Peak measurements @ VIN=115 VAC, full load, TAMB=25 ×C; IC externally biased . . . . . 29

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