AN4243

Designing an application with the L6230

Doc ID 024199 Rev 1

5/29

VBOOT pin) is the same as the three half-bridges. The integrated DMOS have a rated drain-

when a high-side DMOS turns off due to a phase change (OUT1 in Figure 3), if one of the

other outputs (OUT2 in Figure 3) is high, the load current starts flowing in the low-side

freewheeling diode and the SENSE pin sees a negative spike due to a non-negligible

parasitic inductance of the PCB path from the pin to GND. This spike is followed by a stable

a slightly larger voltage due to the forward recovery time of the integrated freewheeling

diode and the forward voltage drop across it. Typical duration of this spike is 30 ns. At the

voltage drop across the high-side (integrated) freewheeling diode, as the current reverses

direction and flows into the bulk capacitor. It turns out that the highest differential voltage is

observed between two OUT pins when a phase change turns a high-side off, and this must

always be kept below 60 V.

Figure 3.

Currents and voltages if a phase change turns a high-side off during off-

time

Figure 4 shows the voltage waveforms at the OUT pins referring to a possible practical

(approximately) and a good PCB layout.

Below ground spike amplitude is -2.65 V for one output, the other OUT pin is at about 55 V.

In these conditions, total differential voltage reaches almost 60 V, which is the absolute

maximum rating for the DMOS. Keeping differential voltage between two output pins within

rated values is a must that can be accomplished with proper selection of bulk capacitor

value and equivalent series resistance (ESR), according to the current peaks and adopting

good layout practices to minimize PCB parasitic inductances.

on- me

off- me

during off- me

a phase change can occur

CB

Parasi c

Inductance

R

Bulk

Capacitor

Equivalent

Circuit

ESR

ESL

PCB Parasi c

Inductance

Current starts

flowing in the third

half bridge

AM16565v1