AN394 - APPLICATION NOTE

2/10

start of the last address bit (A0) of the instruction (signalled by the rising edge of C), and starts to output

the leading zero that precedes the 16-bit data string. The data sheets specify the maximum delay (tCHQL)

between the rising edge of C and the leading zero data bit.

Figure 2. Timing Sequence for a Read Instruction

Since the D driver must remain enabled with the A0 bit for a minimum of tDVCH (the hold time), a bus

conflict occurs whenever the A0 bit is a “1”, as it would be for all odd addressed registers). The conse-

quences are:

– A low impedance path is created between Vcc and ground through the D driver and the on-chip Q output

buffer (as depicted in Figure 3). This short-circuit may produce glitches on the power supply which can

disturb all the circuits on the board.

– The logic level on the D/Q bus is not well-defined: the potential divider chain, so created, can end up

producing a voltage level anywhere between Vcc and 0 V. Thus access to the odd addressed registers

will probably be impossible.

Figure 3. Short-Circuit Created Between Vcc and Ground

Ai02420

D

1

Bus Conflict

Q

C

S

1

0

A5

A4

A3

A2

A1

A0

0

D15 D14 D13 D12 D11 D10

D9

High Impedance

Ai02424

EEPROM Device

D

Q

A0="1"

Common D/Q Bus

D Driver

Low Impedance Path

Output

Buffer

VCC