AN394 - APPLICATION NOTE

4/10

Figure 5. Exponential Charge and Discharge of the Bus Capacitance

As a consequence, the logic level on the D/Q bus is not stable until some time after the rising edge of the

C clock. The delay in reading the bus should be at least 3xRC.

In a typical data sheet for a 5 V device, VOH(min) = 2.4 V and VOL(max) = 0.4 V, so giving a voltage swing

of 2 V. Using the 3xRC approximation, the D/Q bus levels will be:

– logical “1” = 2.3 V minimum after a delay of 3xRC

– logical “0” = 0.5 V maximum after the C rising edge

It might be necessary to reduce the C clock frequency, when shifting the 16 data bits out from the EEP-

ROM during a READ operation, by an amount that is directly related to the RC time constant of the D/Q

bus. All other operations can be performed at the nominal clock rate.

Figures 6, 7, 8 show some experimental examples, plotted from the oscilloscope, with different values of

R and C. In the last example, the maximum clock frequency is: 1/(3xRC) = 100 kHz, assuming that the D/

Q bus is sampled by the Q receiver circuitry just before the rising edge of the C clock.

Ai02422

0

RC

2xRC

3xRC

63%

RC = Time Constant

86%

95%

0

RC

2xRC

3xRC

5%

13%

37%

% of the

Voltage Swing