μPD46185092B, μPD46185182B, μPD46185362B

R10DS0112EJ0200 Rev.2.00

Page 7 of 35

Nov 09, 2012

(2/2)

Symbol

Type

Description

CQ, CQ#

Output

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to

the synchronous data outputs and can be used as a data valid indication. These signals run

freely and do not stop when Q tristates. If C and C# are stopped (if K and K# are stopped in

the single clock mode), CQ and CQ# will also stop.

ZQ

Input

Output Impedance Matching Input: This input is used to tune the device outputs to the

system data bus impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ, where

RQ is a resistor from this bump to ground. The output impedance can be minimized by

unconnected. The output impedance is adjusted every 20

drifts in supply voltage and temperature. After replacement for a resistor, the new output

impedance is reset by implementing power-on sequence.

DLL#

Input

PLL Disable: When debugging the system or board, the operation can be performed at a

clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =

LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must

Ω or less resistor.

TMS

TDI

Input

IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG

function is not used in the circuit.

TCK

Input

IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function

is not used in the circuit.

TDO

Output

IEEE 1149.1 Test Output: 1.8 V I/O level.

−

buffers.

Supply

Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC

Characteristics for range.

Supply

Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See

Recommended DC Operating Conditions and DC Characteristics for range.

Supply

Power Supply: Ground

NC

−

No Connect: These signals are not connected internally.