μPD46185092B, μPD46185182B, μPD46185362B

R10DS0112EJ0200 Rev.2.00

Page 22 of 35

Nov 09, 2012

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

Pin assignments

Description

TCK

2R

Test Clock Input. All input are captured on the rising edge of TCK and all

outputs propagate from the falling edge of TCK.

TMS

10R

Test Mode Select. This is the command input for the TAP controller state

machine.

TDI

11R

Test Data Input. This is the input side of the serial registers placed between

TDI and TDO. The register placed between TDI and TDO is determined by the

state of the TAP controller state machine and the instruction that is currently

loaded in the TAP instruction.

TDO

1R

Test Data Output. This is the output side of the serial registers placed between

TDI and TDO. Output changes in response to the falling edge of TCK.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

JTAG Input leakage current

0 V

−5.0

+5.0

JTAG I/O leakage current

0 V

−5.0

+5.0

Outputs disabled

JTAG input HIGH voltage

1.3

+0.3

V

JTAG input LOW voltage

−0.3

+0.5

V

JTAG output HIGH voltage

1.6

V

1.4

V

JTAG output LOW voltage

0.2

V

0.4

V