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INTERRUPT HANDLING FOR STR7 MICROCONTROLLERS

occurs before the current interrupt has finished. The likely consequence is that the subroutine

would return incorrectly.

The solution here is to disable IRQs in IRQ mode, save the lr_irq, spsr_irq and r0 to r12 reg-

isters to the IRQ stack, then change processor mode to system mode with IRQ enabled, so

the whole interrupt service routine will be executed in system mode. However, it is crucial that,

at the end of the handler the mode must be switched back to IRQ mode, the pending bit of the

related current served channel is cleared in the IPR register and the Saved Program Status

Register is restored in IRQ mode.

__irq therefore cannot be used to write a re-entrant IRQ handler, only a top level assembler

should be used.

6.4 NESTED INTERRUPT EXAMPLE

The following example shows a top level assembler for nested interrupt handler when an in-

struction is used with IVR.

IRQHandler

SUB

lr,lr,#4

STMFD

sp!,{r0-r12,lr}

MRS

r1,spsr

STMFD

sp!,{r1}

LDR

lr, =ReturnAddress

LDR

pc, = IVR_addr

ReturnAddress

LDR

r0, =EIC_Base_addr

LDR

r2, [r0, #CICR_off_addr]

MOV

r3,#1

MOV

r3,r3,LSL r2

STR

r3,[r0, #IPR_off_addr]

LDMFD

sp!,{r1}

MSR

spsr_cxsf,r1

LDMFD

sp!,{r0-r12,pc}^

T0TIMIIRQHandler

MSR

cpsr_c,#0x1F

STMFD

sp!,{lr}

BL

T0TIMI_IRQHandler

LDMFD

sp!,{lr}

MSR

cpsr_c,#0xD2

MOV

pc,lr

Starting off with a program in System mode (in the case of an interrupt routine) or User mode

(main program), suppose that an IRQ request is received and accepted by the EIC. Once the

current instruction has finished executing, the ARM core switches to IRQ mode, saves the re-

turn address and cpsr to lr_irq and spcr_irq, then jumps to address 0x18 and the instruction in