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INTERRUPT HANDLING FOR STR7 MICROCONTROLLERS

1 EXCEPTION ENTRY AND EXIT

1.1 ENTERING AN EXCEPTION

This first section of this application note gives an introduction to Exception Handling by de-

scribing the basic default configuration of the ARM processors.

When an exception occurs, the ARM processor switches automatically to the ARM state and

to the exception mode, copies the Current Program Status Register (CPSR) into

SPSR_<mode> (where SPSR is the Saved Program Status Register, here in a particular

mode), saves the return address in to LR_<mode>, sets the appropriate CPSR bits. The re-

turn address is stored in the Link Register, LR_<mode> to ensure that normal execution can

resume following the exception handling. Finally, the Program Counter (PC) is set to the

vector address to where the exception can be handled.

After handling the exception, the reverse process needs to be applied where CPSR is restored

from SPSR_<mode> and the PC is restored from LR_<mode>.

Remember that exception handling can only be exited in ARM state, so if previously in Thumb

state, prior to exit the exception, the core should switch states to ARM.

1.2 LEAVING AN EXCEPTION

To return from an exception, a data procession instruction is used however the exact instruc-

tion depends on the exception being handled.

In the ARM state, the use of the S bit normally sets the conditional flag. However, when in priv-

ileged modes, with the S bit set and the PC as the destination register, the instruction will up-

date the PC and copy the SPSR_<mode> into the CPSR. Finally, still in privileged mode, LDM

can be used with the ^ qualifier if LR_<mode> is adjusted before being stacked.

For SWI and Undefined exception handlers

MOVS

pc, lr

For FIQ, IRQ and Prefect Abort exception handlers

SUBS

pc, lr, #4

For Data Abort exception handlers

SUBS

pc, lr, #8

LDM can be used with the ^ qualifier if LR adjusted before being stacked

LDMFD

sp!,{pc}^

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