AN2009 datasheet(13/39 Pages) STMICROELECTRONICS

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PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7MC

Figure 9. Oscilloscope waveforms: Voltage Mode

Note: In speed regulation, the PWM duty cycle value only needs to be correct when starting

the motor. Once the target speed is reached, the PWM duty cycle will be adjusted automati-

cally by the ST7MC.

4.1.2 PWM signal register setting in Voltage mode

In voltage mode, the 12-bit timer is used to set the PWM signal.

Compare 0 registers:

The compare 0 high and low registers are for setting the frequency of the PWM.

COMPARE 0 PRELOAD REGISTER HIGH (MCP0H)

Read/Write (except bits 7:4)

Reset Value: 0000 1111 (0Fh)

Bits 7:4 = Reserved.

Bits 3:0 = CP0H[3:0] Most Significant Bits of Compare 0 preload value.

COMPARE 0 PRELOAD REGISTER LOW (MCP0L)

Read/Write

Reset Value: 1111 1111 (FFh)

Bits 7:0 = CP0L[7:0] Low byte of Compare 0 preload value.

CP0H3 CP0H2 CP0H1 CP0H0

CP0L7 CP0L6 CP0L5 CP0L4 CP0L3 CP0L2 CP0L1 CP0L0

1. Current in Phase A

2. Signal on High Side

Triple Half Bridge

Configuration

3. Current Limitation

4. Current Feedback

3. Current Limitation

Switch of Phase A on

AN2009 数据表(PDF) 13 Page - STMicroelectronics