AN2523

Register bit definition changes

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Register bit definition changes

A few of the STR91xF control register bits have been become "don't care" bits as their

function are hardwired in the STR91xFA. You can keep the "don't care" configuration bits in

your code, they no longer has any impact on the device operation.

Many of the reserved bits in the EMI_BCRx register and the SCU_GPIOEMI register have

been activated to support the PSRAM (synchronous) mode of the enhanced EMI bus. If you

have kept these bits in the default reset value, there will be no impact when you switch to the

STR91xFA devices.

Table 2.

Register Bit Changes

Item

Peripheral/

Function

STR91xF

STR91xFA

1

FMI Bus

Control/PFQ

configuration

FMI_CR Register bit 0 -

configure PFQ_FIFO size

0: PFQ FIFO size is 4 words

1: PFQ FIFO size is 8 words

reset to 0

FMI_CR Register bit 0 - configurePFQ_FIFO size

The bit becomes "don't care" in STR91xFA, the

FIFO size defaults to 8 words and cannot be

changed.

2

System

Controller/PLL

Configuration

SCU_PLLCONF Register: P, N

and M reset values are:

P = 0,

N = 18h

M = 19h

(P, N, M configure the PLL clock

frequency to 48 MHz)

SCU_PLLCONF Register: P, N and M

reset values are: P = 03h,N = C0h M = 19h (The

new P, N, M values generate the most stable 48

MHz PLL clock frequency)

3

Watch Dog Timer

SCU_PCGR1 Register bit 12 -

0: Clock to the Watchdog Block is

stopped (default)

1: Clock to the Watchdog Block is

running

SCU_PCGR1 Register bit 12 -

This bit becomes "don't care". The system clock to

the Watchdog Block is always running. (Note: this is

not the Watch Dog timer clock)

SCU_PRR1 Register bit 12 - 0:

The Watchdog Block is held in

reset (default)

1: The Watchdog Block is not

held in reset

SCU_PRR1 Register bit 12 -

This bit becomes "don't care". The Watchdog Block

can not be held in reset.