AN2549

Modified registers

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3

Modified registers

3.1

XPERCON register

In the ST10F272Z2, new bits have been added with regards to the additional XPeripherals.

The XPERCON register allows the XBus peripherals to be separately selected and made

visible to the user by means of the corresponding bits. If an XBus peripheral is not selected

(not activated with a bit of XPERCON) before the XPEN bit in SYSCON is set, the

corresponding address space, port pins and interrupts are not occupied by the peripheral,

and thus this peripheral is not visible and not available.

ST10F269Zx: XPERCON (F024h /

12h)

SFR

Reset value: --05h

15

14

13

12

11

10

98765

4321

0

Reserved

RTC

EN

CAN2

EN

CAN1

EN

-

R/W

R/W

R/W

R/W

R/W

ST10F272Z2: XPERCON (F024h/12h)

SFR

Reset value: -005h

15

14

13

12

11

10

98765

4321

0

Reserved

XI2C

EN

XSSC

EN

XASC

EN

Res.

RTC

EN

CAN2

EN

CAN1

EN

-

R/W

R/W

R/W

R/W

R/W

-

R/W

R/W

R/W

R/W

R/W

Table 15.

XPERCON register description

Bit

Bit name

Function

15:11

-

Reserved

10

XMISCEN

XBUS Additional Features Enable Bit

0: Accesses to the Additional Miscellaneous Features is disabled.

1: The Additional Features are enabled and can be accessed.

9XI2CEN

XI 2 C Enable Bit

0: Accesses to the on-chip XI 2 C are disabled, external access performed.

1: The on-chip XI 2 C is enabled and can be accessed.

8

XSSCEN

XSSC Enable Bit

0: Accesses to the on-chip XSSC are disabled, external access performed.

1: The on-chip XSSC is enabled and can be accessed.

7

XASCEN

XASC Enable Bit

0: Accesses to the on-chip XASC are disabled, external access performed.

1: The on-chip XASC is enabled and can be accessed.

6XPWMEN

XPWM Enable

0: Accesses to the on-chip XPWM module are disabled, external access

performed.

1: The on-chip XPWM module is enabled and can be accessed.

5-

Reserved