AN3023

Configuring ADC registers for conversion

Doc ID 16113 Rev 1

13/23

the CONT bit is cleared while conversion is ongoing, conversion stops the next time the last

channel has been converted.

Example 4

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Continuous scan from AIN0 to AIN3 channel

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Right alignment

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Starting ADC by TIM1

For Example 4, the ADC registers should be configured as follows:

ADC_CR1:SPSEL[2:0] = 000

ADC_CSR:CH[3:0] = 0011

ADC_CR1:ADON = 1

ADC_CR1:CONT = 1

ADC_CR2:SCAN = 1

ADC_CR2:ALIGN = 1

ADC_CR2:EXTSEL[1:0] = 00

ADC_CR2:EXTTRIG = 1

Timer initialization for trigger output: The timer has to be configured in PWM mode, with a

period of at least 7 µs, in order to guarantee a good ADC conversion.

PWM signal @50 kHz (period = 20 µs)

TIM1_SMCR:MSM = 1

TIM1_CR2:MMS[6:4] = 100

TIM1_CR1:CEN = 1

ADC conversion will start at each rising edge event of OC1REF signal

Wait (ADC_CSR:EOC = 1)

Read the result of the current conversion from ADC_DBxRH and ADC_DBxRL registers

(x = 0..3) before of the end of next conversion. The OVR flag is set if one of the buffer

registers is overwritten.

Note:

1

In scan mode, do not use the bit manipulation instruction (BRES) to clear the EOC flag

because it performs a read-modify-write on the whole ADC_CSR register, reading the

current channel number from the CH[3:0] register and writing it back. This changes the last

channel number for the scan sequence. The correct way to clear the EOC flag in continuous

scan mode is to load a byte in the CSR register from a RAM variable, clearing the EOC flag

and reloading the last channel number for the scan sequence.

2

When using scan mode, it is not possible to use channels AIN0 to AINn in output mode

because the output stage of each channel is disabled when it is selected by the ADC

multiplexer.