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AN3023 数据表(PDF) 3 Page - STMicroelectronics

部件名 AN3023
功能描述  Using the analog-to-digital converter of the STM8A microcontroller
PDF  23 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

AN3023 数据表(HTML) 3 Page - STMicroelectronics

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AN3023
ADC hardware description
Doc ID 16113 Rev 1
3/23
1
ADC hardware description
1.1
General properties
STM8A family microcontrollers include an analog-to-digital converter which has up to 16
multiplexed inputs. The ADC resolution is 10 bits. The number of external analog inputs
depends on the package size of the particular STM8A family device.
The ADC is a successive approximation analog-to-digital converter. Conversion can be
performed in continuous mode or single mode. The digital result is then stored in registers.
Because the ADC resolution is 10 bits and the ADC data register length is 16 bits, the
analog-to-digital converter result is stored in two 8-bit registers, and the data is either right
or left aligned (this is selectable).
The event used to start conversion can be generated by software or by the STM8A
microcontroller's internal timer 1 and timer 2(a) (any type of timer event can be used). The
start of A/D conversion can also be triggered by an external pin.
The reference voltage for the analog-to-digital converter depends on the package. It comes
either from an external source—in this case the reference must be connected to two
external pins—or is connected internally to analog power supply pins. The value of this
reference voltage is limited to within the range from 2.75 V up to the voltage applied on the
VDDA input. The measured voltage must be between VREF+ and VREF−. Resolution can be
increased by so-called analog zooming—using a smaller reference voltage around the
range of values to be measured.
If needed, an interrupt can be generated at the end of conversion and if an analog watchdog
event occurred.
The analog-to-digital converter is driven by a clock derived from the MCU master clock
through a programmable divider. This allows you to select the ADC clock speed according to
your application requirements.
a.
Trigger feature available on selected devices



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