ADC hardware description

AN3023

4/23

Doc ID 16113 Rev 1

Figure 1.

ADC block diagram

1.

Refer to STM8A reference manual for ADC registers bit description

EOC

AWD

CH3

CH2

CH1

CH0

-

SP

SEL2

SP

SEL1

SP

SEL0

-

-

CONT ADON

-

EXT

TRIG

EXT

SEL1

EXT

SEL0

ALIGN

-

SCAN

-

DBUF

OVR

ADON

SyncE

ADON

Sync

-

-

-

-

AWDG voltage reference low

AWDG voltage reference high

AWDG Status Register channel [7:0]

AWDG Status Register channel [15:8]

AWDG Enable Register channel [7:0]

AWDG Enable Register channel [15:8]

Interrupt

Analog-to-Digital

Converter

Mux

TIM1

TIM2

General

Purpose

IOs

Prescaler

/2, /3:

/18

CK_ADC

4

2

2

2

Data Buffer

Data Register

Schmitt Trigger Enable TE[7:0]

Schmitt Trigger Enable TE[15:8]

AIN0

AIN15

AIN1

ADC_ETR

EOCIE AWDIE