AN3099

DDR IBIS model selection

Doc ID 16605 Rev 1

9/13

nDDR_MEM_DQS_1, DDR_MEM_DQ [15:0]. For all the other signals ODTEN = 0, ODTA =

1, ODTB = 1.

2.1

Example

The setting of the registers DDR_PAD and MEMCTL_AHB_SET_02 is normally done at

each system boot-up by the XLOADER part of the boot code.

Let’s assume, as an example, that at the end of the boot operation the application reads

these two registers and finds the following values:

●

Register DDR_PAD (Address 0xFCA800F0) = 0x00003AA5.

●

Register MEMCTL_AHB_SET_02 Register (Address 0xFC60002C) = 0x05000202.

The correct model to be selected from the library with the above values is the following:

Table 4.

Relation between the DDR clock signals and the used model

DDR block signal name

IBIS model used for application board

DDR_MEM_CLKP &

DDR_MEM_CLKN

BDCLK_R_IN_xxxxxxxx = BDCLK_R_IN_11000110

DDR_MEM_DQS_0 &

nDDR_MEM_DQS_0

DDR_MEM_DQS_1 &

nDDR_MEM_DQS_1

If READ => BDCLK_R_IN_xxxxxxxx =

BDCLK_R_IN_11000101

If WRITE => BDCLK_R_IN_xxxxxxxx =

BDCLK_R_IN_11000110

DDR_MEM_DQ[15,13,11,9,6,4,2,0]

If READ => BDRES_GNDE_xxxxxxx =

BDRES_GNDE_01001110

If WRITE => BDRES_GNDE_xxxxxxx =

BDRES_GNDE_01001011

DDR_MEM_ADD[14,12,10,8,6,4,2,0]

DDR_MEM_GATE_0

DDR_MEM_DM_1

DDR_MEM_CLKEN

DDR_MEM_CS_1

DDR_MEM_ODT_1

DDR_MEM_BA_1

DDR_MEM_CAS

BDRES_GNDE_xxxxxxx = BDRES_GNDE_01001011

DDR_MEM_DQ[14,12,10,8,7,5,3,1]

If READ => BDRES_VDDE_xxxxxxx =

BDRES_VDDE_01001110

If WRITE => BDRES_VDDE_xxxxxxx =

BDRES_VDDE_01001011

DDR_MEM_ADD[13,11,9,7,5,3,1]

DDR_MEM_GATE_1

DDR_MEM_DM_0

DDR_MEM_CS_0

DDR_MEM_ODT_0

DDR_MEM_BA_0

DDR_MEM_BA_2

DDR_MEM_RAS

DDR_MEM_WE

BDRES_VDDE_xxxxxxx = BDRES_VDDE_01001011