PL_CLK & PL_GPIO IBIS model selection

AN3099

2/13

Doc ID 16605 Rev 1

1

PL_CLK & PL_GPIO IBIS model selection

The I/O signals of the PL_CLK & PL_GPIO interface form two main groups.

Please refer to the following table for the I/O signals and the associated model name.

Each model group name contains a set of models depending upon the value of the 5 bits

xxxx for the selected PL_GPIO [….] or PL_CLK [….] signals.

Table 1.

Relation between the PL_.... block signals and the used model

PL_.... block signal

name

IBIS model group name

PL_CLK[4:1]

BDPROG_2ROWS_xxxxx

xxxxx = MODEOP0 MODEOP1 DRV0 DRV1 SL

PL_GPIO[97:95]

PL_GPIO[92:85]

PL_GPIO[82:73]

PL_GPIO[70:69]

PL_GPIO[67:58]

PL_GPIO[56:53]

PL_GPIO[50:43]

PL_GPIO[40:33]

PL_GPIO[30:25]

PL_GPIO[22:19]

PL_GPIO[16:11]

PL_GPIO[8:5]

PL_GPIO[2:1]

BDPROG_2ROWS_xxxxx

xxxxx = MODEOP0 MODEOP1 DRV0 DRV1 SL

PL_GPIO[94:93]

PL_GPIO[84:83]

PL_GPIO[72:71]

PL_GPIO[68]

PL_GPIO[57]

PL_GPIO[52:51]

PL_GPIO[42:41]

PL_GPIO[32:31]

PL_GPIO[24:23]

PL_GPIO[18:17]

PL_GPIO[10:9]

PL_GPIO[4:3]

PL_GPIO[0]

BDPROG_STD_xxxxx

xxxxx = MODEOP0 MODEOP1 DRV0 DRV1 SL