AN3140

General purpose timers (GPTs) in SPEAr3xx

Doc ID 16997 Rev 1

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General purpose timers (GPTs) in SPEAr3xx

In the SPEAr3xx architecture, there are three different GPT blocks located in the various

subsystems. Each timer block consists of two independent channels, each one with a 16-bit

counter register.

Table 1.

GPTs in SPEAr3xx

Each timer has a READ_Clk, input which is the APB clock (PCLK), and a CNT_Clk, which

can be selected by the user from a list of clock sources.

●

READ_Clk (PCLK): When SPEAr3xx is in normal mode, it takes the input from PLL1

divided by a programmable prescaler, whose reset values impose the ratio 1:2:4 to the

core_clk, HCLK and PCLK clocks. When SPEAr3xx is in slow mode, it takes directly

the input from the OSCI signal.

●

CNT_Clk: The clock source can be selected as either a fixed 48 MHz or the PLL1 itself

divided by a programmable prescaler, which is defined in the PRSC1_CLK_CFG

register (0xFCA8_0044) for GPT1, PRSC2_CLK_CFG register (0xFCA8_0048) for

GPT2 and PRSC3_CLK_CFG register (0xFCA8_004C) for GPT3. The CNT_Clk may

then be further divided by a GPT internal 4-bit prescaler able to divide up to 256 times

(‘/256’).

Figure 1.

GPT clock sources

The following table describes the clock selectors (Clock_Sel) for each GPT.

Subsystem

Base address

GPT1

ARM

0xF000_0000

GPT2

Basic1

0xFC80_0000

GPT3

Basic2

0xFCB0_0000

GPT Ch1

GPT Ch2

Read_CLK

(PCLK)

CNT_Clk

PLL3 (48MHz)

PRSCx_CLK_CFG

PLL1 (332MHz)/

OSCI (24MHz)

HCLK/PCLK

prescaler

MUX

PLL1 (332MHz)

Clock_Sel

int_prsc