AN3140

Reading a free-running timer counter

Doc ID 16997 Rev 1

5/14

2

Reading a free-running timer counter

When the GPT interrupt is enabled, the interrupts generated at each timer wrap-around

condition are always triggered at the right frequency, however reading the timer counter

when the timer itself is active and free-running may present some difficulties which are

described below.

In a simplified scenario, a hardware timer block can be seen just as a simple counter

register with two input clocks:CNT_Clk for incrementing/decrementing the counter and

READ_Clk for synchronizing the READ accesses of the bus the timer is connected to.

Figure 2.

Simplified timer

The two clocks can be either synchronous, coming from the same source PCLK, or

completely asynchronous, for example coming from two different sources.

When the two clocks involved in the scenario are asynchronous, then the value retrieved by

the CPU in a read counter operation is unpredictable, and might be completely different from

the real value in the register.

The situation is due to the fact that the READ_Clk is sampling the counter bits while they are

in a transitioning, unstable phase.

Figure 3.

Sampling a counter bit in an unstable state

The above scenario may take place during any kind of transition (0->1 or 1->0) and for any

bit in the register.

If one of the bits impacted has a large weight (significant position) in the counter, then the

difference between the value returned in the read transaction and the real value of the

counter can be very large.

CNT_Clk

0

0

1

0

1

…

READ_Clk

CNT_Clk

READ_Clk

Bit_N

t0 t1 t2

start a 0->1 transitioning

sampled in an unstable state