AN3270

AES hardware accelerator operation modes

Doc ID 17919 Rev 2

3/23

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AES hardware accelerator operation modes

The Advanced Encryption Standard (AES) hardware accelerator can be used to encrypt

(encipher) and decrypt (decipher) 128-bit blocks using a 128-bit key length. It is a fully

compliant implementation of the AES standard as defined by Federal Information

Processing Standards publication (FIPS PUB 197, 2001 November 26).

Figure 1.

AES hardware accelerator

The main features of the built in AES hardware accelerator STM8L16x devices are:

●

Both encryption and decryption with compliance to FIPS using a 128-bit key

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Key derivation for decryption

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892 clock cycles to encrypt or decrypt one 128-bit block

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Read and write error detection with interrupt capability

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AES Computation Complete interrupt capability

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Automatic data flow control with support of direct memory access (DMA) using 2

channels: one for incoming data, the other for outgoing data.

The AES hardware accelerator provides four modes of operation:

1.

Encryption mode

2.

Decryption mode (using decryption key)

3.

Key derivation mode

4.

Key derivation and decryption mode (using encryption key)

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