AES hardware accelerator operation modes

AN3270

4/23

Doc ID 17919 Rev 2

Once configured and enabled, the AES goes through three phases:

●

Input phase: data (plain text, cipher text or key) are written in the AES Data Input

Register (AES_DINR). This phase can be carried-out either by the CPU or by Direct

Memory Access (DMA).

●

Computation phase: the AES hardware accelerator performs the AES operation

(encryption, decryption...). Once this phase ends, the Computation Complete Flag is

set. An interrupt can be generated if enabled using Computation Complete Interrupt

Enable bit (CCIE).

●

Output phase: the application can read the Data Output Register (AES_DOUTR). Like

the input phase, this task can be performed by the CPU or by DMA.

1.1

AES encryption mode

In this mode, the AES accelerator performs the encryption of a 128-bit plain text using the

provided 128-bit key to compute the cipher text.

In the example below, the plain text “STM32L and STM8L” is encrypted using the key “ultra-

low power.”. The cipher text, computed by the AES hardware accelerator, in ASCII format is

"ö!?ø¯Àþ6¸•rËѨ" and in hex format is “22 F6 21 81 F8 AF C0 FE 03 36 B8 95 72 CB D1 A8”.

Figure 2.

AES hardware accelerator: encryption mode

The AES takes 892 clock cycles to encrypt one 128-bit block.

To perform text encryption, follow the algorithm given in the flowchart below.

MS19716V1

AES hardware accelerator:

Encryption mode

ö!ø¯Àþ?6¸•rËѨ

128-bit cipher text

Encryption Key:

“ultra-low power.”

STM32L and STM8L

128-bit plain text