AN3317

Via padstack

Doc ID 18249 Rev 2

7/22

3

Via padstack

Ensure that via padstack dimensions support density requirements.

While meeting PCB fabrication tolerances, make antipad diameters small enough to allow

an adequate copper web between the clearance holes of adjacent vias.

3.1

Part orientation and placement

To optimize routing and signal integrity, give the DRAM placement and orientation priority

over other unassociated components.

Orient DRAM components such that the DQ balls face the controller.

Define a dedicated area for the memory system that encloses all components associated

with the memory system and excludes all other components and signal routing.