AN3317

DDR memory interface

Doc ID 18249 Rev 2

9/22

5

DDR memory interface

5.1

DRAM power decoupling

A low impedance, wide bandwidth power delivery network (PDN) is critical for the proper

operation of high-speed ICs such as SPEAr and DDR memory. If the PDN impedance is too

high or does not have sufficient bandwidth, logic performance is affected. This results in

ground and rail bounce, and slower rise and fall times of both IO and internal logic, which in

turn results in delayed timing of events. These timing delays from inadequate ground and

power subtract directly from the specified timing budget, which can result in interface failure.

To achieve a low impedance wide bandwidth power delivery network, use the appropriate

decoupling capacitors and capacitor layout. A large portion of the power delivery network’s

frequency spectrum is above the decoupling capacitor’s series resonant frequency, where

they are inductive. The PCB layout for decoupling capacitors is also inductive, and is a

larger inductance than that of the capacitors themselves.

For IC core voltage and high-speed IO supplies (such as DDR) select:

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capacitors with low inherent inductance (small package size)

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a lossy dielectric

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a PCB layout that provides the lowest possible inductance

Use as many capacitors as can fit in the space available. This creates many parallel paths,

reducing the overall inductance seen by the IC. A small capacitor package size and a small

layout enable this.

5.1.1

Capacitors

See also, Appendix A: Low-inductance capacitor layout in high-frequency applications

Package: Use 0402 package size to minimize mounting inductance. The small 0402

package also frees board space, which is essential in high density areas for more

decoupling capacitors and signal routing.

Capacitance: 100 nF or larger

A few capacitors of smaller value will probably be necessary for plane resonance

suppression. The correct values for these depend on the board layout and stack up, and

must be determined individually for each unique PC board.

Dielectric: X7R or X5R dielectric. Do not use Y5V dielectric for decoupling mid-frequency

applications.

Decoupling capacitor layout

Decoupling capacitors layout is extremely important to minimize the induction loop formed

between the capacitor and the IC power and ground balls. Using the layout guidelines that

follow can reduce the capacitor mounting induction loop by 50% or more over a layout with

vias at the end of the capacitor lands. If space allows, a second pair of vias on the opposite

side of the capacitor will reduce the inductance further. Closely follow the decoupling layout

example on page 10.

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Place vias on the side of the capacitor lands, not on the ends.

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Locate vias at minimum keepout distance, and connect them to the capacitor lands with

a wide trace – at least as wide as the via pad.