AN3317

Power integrity

Doc ID 18249 Rev 2

5/22

1

Power integrity

One of the most important requirements of a reliable high-speed memory interface, and

most commonly underestimated, is a low impedance, wide bandwidth power supply at the

power and ground balls of the devices.

Achieving the necessary performance requires minimizing all parasitic inductances found in

power delivery and grounding connections, exploiting various techniques to provide low

impedance paths, and attention to controlling plane resonances.

A solid, unbroken ground plane located close to the high-speed devices in the PCB layer

stack is critical. The ground plane must not have large gaps anywhere in the area of the

interface. Be especially aware of overlapping antipads that can create an extended gap in

the internal plane layers.

A power plane closely spaced to the ground plane greatly aids in high-frequency decoupling

by providing a low inductance path between a capacitor and the device's power balls.

Use a low-inductance layout for all high-frequency decoupling capacitors.