AN3422 datasheet(21/52 Pages) STMICROELECTRONICS

21 / 52 page

AN3422

Peripheral migration

Doc ID 018976 Rev 2

21/52

enable/disable, 64-bit access enable/disable...) or/and the PLL parameters

configuration:

If the HSE or HSI is used directly as system clock source, in this case only the

Flash parameters should be modified.

If PLL (clocked by HSE or HSI) is used as system clock source, in this case the

Flash parameters and PLL configuration need to be updated.

Table 7 below provides an example of porting a system clock configuration from F1 to L1

series:

–

STM32F105/7 Connectivity Line running at maximum performance: system clock

at 72 MHz (PLL, clocked by the HSE, used as system clock source), Flash with 2

wait states and Flash prefetch queue enabled.

–

L1 series running at maximum performance: system clock at 32 MHz (PLL,

clocked by the HSE, used as system clock source), Flash with 1 wait state, Flash

prefetch and 64-bit access enabled.

As shown in the table below, only the Flash settings and PLL parameters (code in Bold

Italic) need to be rewritten to run on L1 series. However, HSE, AHB prescaler and system

clock source configuration are left unchanged, and APB prescalers are adapted to the

maximum APB frequency in the L1 series.

Note:

The source code presented in the table below is intentionally simplified (time-out in wait loop

removed) and is based on the assumption that the RCC and Flash registers are at their

reset values.

For STM32L1xx you can use the clock configuration tool,

STM32L1xx_Clock_Configuration.xls, to generate a customized system_stm32l1xx.c file

containing a system clock configuration routine, depending on your application

requirements. For more information, refer to AN3309 “Clock configuration tool for

STM32L1xx microcontrollers”

AN3422 数据表(PDF) 21 Page - STMicroelectronics