AN3422 datasheet(31/52 Pages) STMICROELECTRONICS

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AN3422

Peripheral migration

Doc ID 018976 Rev 2

31/52

Alternate function mode

In STM32F1 series

The configuration to use an I/O as alternate function depends on the peripheral mode

used, for example the USART Tx pin should be configured as alternate function push-

pull while USART Rx pin should be configured as input floating or input pull-up.

To optimize the number of peripheral I/O functions for different device packages

(especially with those with low pin count), it is possible to remap some alternate

functions to other pins by software, for example the USART2_RX pin can be mapped

on PA3 (default remap) or PD6 (by software remap).

In STM32L1 series

Whatever the peripheral mode used, the I/O must be configured as alternate function,

then the system can use the I/O in the proper way (input or output).

The I/O pins are connected to on-chip peripherals/modules through a multiplexer that

allows only one peripheral’s alternate function to be connected to an I/O pin at a time.

In this way, there can be no conflict between peripherals sharing the same I/O pin.

Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that

can be configured through the GPIOx_AFRL and GPIOx_AFRH registers:

–

After reset all I/Os are connected to the system’s alternate function 0 (AF0)

–

The peripheral alternate functions are mapped by configuring AF1 to AF13

–

Cortex-M3 EVENTOUT is mapped by configuring AF15

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate

functions mapped on different I/O pins to optimize the number of peripheral I/O

functions for different device packages, for example the USART2_RX pin can be

mapped on PA3 or PD6 pin

Note:

Please refer to the “Alternate function mapping” table in the STM32L15x datasheet for the

detailed mapping of the system and the peripheral alternate function I/O pins.

Configuration procedure

–

Configure the desired I/O as an alternate function in the GPIOx_MODER register

–

Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,

GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively

–

Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register

4.8

EXTI source selection

In STM32F1 the selection of EXTI line source is performed through EXTIx bits in

AFIO_EXTICRx registers, while in L1 series this selection is done through EXTIx bits in

SYSCFG_EXTICRx registers.

Only the mapping of the EXTICRx registers has been changed, without any changes to the

meaning of the EXTIx bits. However, the maximum range of EXTIx bits values is 0b0101 as

only 6 GPIO ports are supported in L1 (in F1 series the maximum value is 0b0110).

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