AN3422 datasheet(39/52 Pages) STMICROELECTRONICS

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AN3422

Firmware migration using the library

Doc ID 018976 Rev 2

39/52

implementation of SystemInit() function used to configure the microcontroller system at

start-up and before branching to the main() program.

Note:

For STM32L1xx you can use the clock configuration tool,

STM32L1xx_Clock_Configuration.xls, to generate a customized SystemInit() function

depending on your application requirements. For more information, refer to AN3309 “Clock

configuration tool for STM32L1xx microcontrollers”

Peripheral access configuration: as presented in section 4.4: RCC you need to call

different functions to [enable/disable] or [enter/exit] the peripheral [clock] or [from reset

mode]. For example, GPIOA is mapped on AHB bus on L1 series (APB2 bus on F1

series), to enable its clock you have to use the

RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);

function instead of:

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);

in the F1 series. Refer to Table4 on page15 for the peripheral bus mapping changes

between L1 and F1 series.

Peripheral clock configuration

USB FS Device: in STM32L1 series the USB FS Device require a frequency of 48

MHz to work correctly. The following is an example of the main PLL configuration

to obtain 32 MHz as system clock frequency and 48 MHz for the USB FS Device.

/* PLL_VCO = HSE_VALUE * PLL_MUL = 96 MHz */

/* USBCLK = PLL_VCO / 2= 48 MHz */

/* SYSCLK = PLL_VCO * PLL_DIV = 32 MHz */

RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);

/* Enable PLL */

RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0)

{

}

/* Select PLL as system clock source */

RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock source */

while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)

{

}

...

/* Enable USB FS Device's APB1 interface clock */

RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);

ADC: in STM32L1 series the ADC features two clock schemes:

–

Clock for the analog circuitry: ADCCLK. This clock is generated always from the

HSI clock divided by a programmable prescaler that allows the ADC to work at

fHSI/1, /2 or /4. This configuration is done using the ADC registers.

–

Clock for the digital interface (used for register read/write access). This clock is

equal to the APB2 clock. The digital interface clock can be enabled/disabled

through the RCC APB2 peripheral clock enable register (RCC_APB2ENR).

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