PM0063

Reading/programming the STM32F100xx embedded Flash memory

Doc ID 16211 Rev 2

13/30

Also a bus error is returned on a wrong key sequence. This is done after the first write cycle

if KEY1 does not match, or during the second write cycle if KEY1 has been correctly written

but KEY2 does not match. The FPEC block and FLASH_CR register can be locked by the

user’s software by writing the LOCK bit of the FLASH_CR register to 1. In this case, the

FPEC can be unlocked by writing the correct sequence of keys into FLASH_KEYR.

2.3.3

Main Flash memory programming

The main Flash memory can be programmed 16 bits at a time. The program operation is

started when the CPU writes a half-word into a main Flash memory address with the PG bit

of the FLASH_CR register set. Any attempt to write data that are not half-word long will

result in a bus error response from the FPEC. If a read/write operation is initiated during

programming, (BSY bit set), the CPU stalls until the ongoing main Flash memory

programming is over.

Figure 1.

Programming procedure

Standard programming

In this mode the CPU programs the main Flash memory by performing standard half-word

write operations. The PG bit in the FLASH_CR register must be set. FPEC preliminarily

reads the value at the addressed main Flash memory location and checks that it has been

erased. If not, the program operation is skipped and a warning is issued by the PGERR bit in

FLASH_SR register (the only exception to this is when 0x0000 is programmed. In this case,

the location is correctly programmed to 0x0000 and the PGERR bit is not set). If the

addressed main Flash memory location is write-protected by the FLASH_WRPR register,

the program operation is skipped and a warning is issued by the WRPRTERR bit in the

Read FLASH_CR_LOCK

FLASH_CR_LOCK

= 1

Yes

No

Yes

No

Perform unlock sequency

Write FLASH_CR_PG to 1

Perform half-word write at the

desired address

FLASH_SR_BSY

= 1

Check the programmed value

by reading the programmed

address

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