PM0073

Reading/programming the STM32Wxxx embedded Flash memory

Doc ID 17766 Rev 5

13/34

2.1.3

Flash access controller

Mainly, this block is a simple arbiter between the read requests of the prefetch/I-code and D-

Code interfaces.

D-Code interface requests have priority over I-Code requests.

2.2

Flash program and erase controller (FPEC)

The FPEC block handles the program and erase operations of the Flash memory. The

FPEC consists of seven 32-bit registers.

●

FPEC key register (FLASH_KEYR)

●

Option byte key register (FLASH_OPTKEYR)

●

Flash control register (FLASH_CR)

●

Flash status register (FLASH_SR)

●

Flash address register (FLASH_AR)

●

Option byte register (FLASH_OBR)

●

Write protection register (FLASH_WRPR)

An ongoing Flash memory operation will not block the CPU as long as the CPU does not

access the Flash memory.

Note:

These registers can be accessed for writing only in Privileged mode.

2.2.1

Key values

The key values are as follows:

●

RDPRT key = 0x00A5

●

KEY1 = 0x45670123

●

KEY2 = 0xCDEF89AB

2.2.2

Unlocking the Flash memory

After reset, the FPEC block is protected. The FLASH_CR register is not accessible in write

mode. An unlocking sequence should be written to the FLASH_KEYR register to open up

the FPEC block. This sequence consists of two write cycles, where two key values (KEY1

and KEY2) are written to the FLASH_KEYR address (refer to Section 2.2.1: Key values for

key values). Any wrong sequence locks up the FPEC block and FLASH_CR register until

the next reset.

Also a bus error is returned on a wrong key sequence. This is done after the first write cycle

if KEY1 does not match, or during the second write cycle if KEY1 has been correctly written

but KEY2 does not match. The FPEC block and FLASH_CR register can be locked by the

user’s software by writing the LOCK bit of the FLASH_CR register to 1. In this case, the

FPEC can be unlocked by writing the correct sequence of keys into FLASH_KEYR.