PM0073 datasheet(25/34 Pages) STMICROELECTRONICS

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PM0073

Doc ID 17766 Rev 5

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In this section, the following abbreviations are used:

Note:

The Flash memory registers have to be accessed by 32-bit words (half-word and byte

accesses are not allowed).

3.1

Flash access control register (FLASH_ACR)

Address offset: 0x00

Reset value: 0x0000 0031

Table 11.

Abbreviations

Abbreviation

Meaning

read/write (rw)

Software can read from and write to these bits.

read-only (r)

Software can only read these bits.

write-only (w)

Software can only write to this bit. Reading the bit returns the reset value.

read/clear (rc_w0)

Software can read as well as clear this bit by writing ‘0’. Writing ‘1’ has no

effect on the bit value.

read/set (rs)

Software can read as well as set this bit. Writing ‘0’ has no effect on the bit

value.

Reserved (Res.)

Reserved bit, must be kept at reset value.

Reserved

PRFT

HLF

CYA

LATENCY

rrw

Bits 31:6 Reserved, must be kept cleared.

Bit 5

PRFTBS: Prefetch buffer status

This bit provides the status of the prefetch buffer.

0: Prefetch buffer is disabled

1: Prefetch buffer is enabled

Bit 4

PRFTBE: Prefetch buffer enable

0: Prefetch is disabled

1: Prefetch is enabled

Bit 3

HLFCYA: Flash half cycle access enable

0: Half cycle is disabled

1: Half cycle is enabled

Bits 2:0

LATENCY: Latency

These bits represent the ratio of the FCLK period to the Flash access time.

000: Zero wait state, if FCLK = SCLK

001: One wait state, if FCLK = SCLK/2

010: Two wait states

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