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PM0073 数据表(PDF) 31 Page - STMicroelectronics |
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PM0073 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 34 page ![]() PM0073 Register descriptions Doc ID 17766 Rev 5 31/34 3.10 Flash controller clock status register (FLASH_CLKSR) Address: 0x40004030 Reset value: 0x0000 0000 Note: This register is present in wireless line devices only. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98765432 10 Reserved rr Bits 31:2 Reserved, must be kept cleared. Bit 1 BSY: Indicates FPEC is busy; therefore, keeps FPEC_CLK enabled. Note: This bit is read-only. Bit 0 ACK: Indicates FPEC_CLK (rc10mck in FLITF) is running and FCLK is 12 MHz. Note: This bit is read-only. |
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