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LTC2953 数据表(PDF) 13 Page - Linear Technology |
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LTC2953 数据表(HTML) 13 Page - Linear Technology |
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13 / 20 page ![]() LTC2953 13 2953f PUSH BUTTON CONTROL Power On Sequence To enable system power, the push button input ( ⎯P⎯B) must be held low continuously for 32ms (tDB, ON). Once the enable output (EN/ ⎯E⎯N) is asserted, the LTC2953 starts a 512ms internal timer (tKILL, ON BLANK). The ⎯K⎯I⎯L⎯L input must be driven high within this 512ms window. This blank- ing time represents the maximum time allowed for the system to power up and initialize the circuits driving the ⎯K⎯I⎯L⎯L input. If ⎯K⎯I⎯L⎯L remains low at the end of the blanking period, the enable output is released (see “Aborted Power On Sequence” section). Figure 9 shows a normal power on sequence. APPLICATIONS INFORMATION Short Pulse Interrupt To interrupt the μP, either ⎯P⎯B or UVLO must be low for at least 32ms (tDB, OFF). This signals the μP either that a user has pressed the push button or that the supply is running low. The μP would then perform power down and housekeeping tasks and assert ⎯K⎯I⎯L⎯L low when done. This in turn releases the enable output, thus shutting off system power. See Figure 10. Note that either ⎯P⎯B or UVLO can control the power down sequence, but not both at the same time. For example, if both ⎯P⎯B and UVLO are high and the user presses the push button, ⎯P⎯B will be active and UVLO will be ignored until ⎯P⎯B is released or the power down sequence is complete. Forced Power Off Sequence The LTC2953 provides a failsafe feature that allows a user to manually force a system power down. For cases when the μP fails to respond to the interrupt signal, the user can force a power down by pressing and holding either the push button or the UVLO inputs low. The length of time required to release the enable output is given by a fixed internal 64ms delay (tPD, Min) plus an adjustable power down timer delay (tPDT). The adjustable delay is set by placing an external capacitor on the PDT pin. Use the following equation to calculate the capacitance for the desired extra delay. CPDT is the PDT pin external capacitor: CPDT = 1.56E-4 [μF/ms] • (tPDT – 1ms) See Figure 11. tDB, ON tKILL, ON BLANK PB KILL EN (LTC2953-1) 2953 F09 PB, UVLO AND KILL IGNORED DO NOT CARE SYSTEM SETS KILL HIGH tDB, OFF tINT, Min PB OR UVLO KILL EN (LTC2953-1) INT 2953 F10 SHORT PULSE DO NOT CARE SYSTEM SETS KILL LOW SYSTEM POWER OFF Note that only the push button input can enable system power. The LTC2953 provides two enable output polarities to allow DC/DC converter control (LTC2953-1) and external power PFET control (LTC2953-2). PB OR UVLO EN (LTC2953-1) PDT 2953 F11 16 CYCLES LONG PULSE tPDT tPD, Min Figure 10. Power Off Interrupt Timing Figure 11. Forced Power Off Timing with Adjustable Delay (See Figure 5 for More Details) Figure 9. Power On Timing (UVLO > 0.55V) |
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