AN4101

Introduction to the LIN bus

Doc ID 23127 Rev 1

7/21

2.4

LIN physical layer

The LIN bus is single-wire, and is connected via a pull-up resistor to the battery voltage

There are two possible bus states:

●

dominant

●

recessive

The LIN bus does not need to resolve bus collisions, since only one message is allowed on

the bus at a time. This guarantees a deterministic system with known latency times.

The default state is recessive. A dominant state occurs when the transmitter pulls down the

bus line. All LIN transmitters operate as and gates, which means that they must all be in a

recessive state for the bus to be in a recessive state.

In Figure 3, Rx and Tx signals refer to the microcontroller USART or LINUART signals, while

Figure 3.

LIN bus circuit diagram

MSv31515V1

Rx

Tx

Master ECU

V BUS

V SUP

V Shift_BAT

1kΩ

30 kΩ

Transceiver IC

D ser_int

V GND_ECU

V BATTERY

V BATTERY

V GND_BATTERY

V BAT

V Shift_GND

V BAT

V SUP : Internal supply for electronics

D ser_master