13

LT1786F

value (see Block Diagram). A STOP condition is optional.

The command code and data byte are defined with the

following format:

Command Code

7

6 5

4 3 2 1

0

76

54

32

10

SHDN X X X X X X X

D5 D4 D3 D2 D1 D0 X

X

SHDN: 0 for normal operation, 1 for shutdown

D5 to D0: DAC Data Byte Bits, D5 is the Most Significant Bit

START and STOP Conditions

At the beginning of any SMBus communication, the mas-

ter must transmit a START condition by switching SDA

from high to low while SCL is high. When a master has

finished communicating with a slave device, a STOP

condition is issued by switching SDA from low to high

while SCL is high. The SMBus is then free for communi-

cation with another SMBus device.

Early STOP Conditions

The LT1786F recongnizes a STOP condition at any point in

the SMBus communication sequence. If the STOP occurs

prematurely before the data byte is acknowledged in the

Write Byte protocol, the DAC output current value is not

updated; otherwise internal register C is updated with the

new data and the DAC output current changes

correspondingly.

The Slave Address

The LT1786F responds to one of two 7-bit addresses. The

first five bits have been factory programmed to 01011. The

last two address bits are programmed by the user by tying

ADR

SMBus ADDRESS

DAC POWER-UP VALUE

GND

0101101

Zero Scale

0101100

Midscale

Data Byte

6-Bit Current Output DAC

The 6-bit current output DAC is guaranteed monotonic and

is digitally adjustable in 63 equal steps. On power-up, if

Block Diagram) resets to 100000B and the DAC output is

set to midrange. On power-up, if ADR connects to ground,

register C resets to 000000B and the DAC output is set to

current is trimmed to

±2% at room temperature and ±4%

over the commercial temperature range.

Shutdown

Three methods may be employed to shut down the LT1786F

(see Block Diagram).

The LT1786F enters SMBus suspend mode if a logic low

level is applied to the SMBSUS pin or a logic high level is

applied to Bit 7 in the Command Byte of the SMBus

communication sequence. In SMBus suspend mode, sup-

ply current typically drops to 40

µA and the last output

current setting is internally retained. The DAC resumes

this level upon its return to normal operation. Enabling an

SMBus suspend condition also turns on an open-drain

N-channel MOSFET which pulls the SHDN pin low. The

N-channel device sinks up to 1.6mA at the SHDN pin and

its logic low level is guaranteed to less than 0.4V.

The LT1786F enters regulator shutdown mode if a logic

low level is applied to the SHDN pin. In this mode, supply

current typically drops to 150

µA, the switching regulator

circuitry is shut down and the DAC is kept alive. The DAC

output current setting is maintained. This feature can be

used to program the DAC to a desired output current level

(other than the preset zero-scale or midscale level defined

by the selected SMBus address) before allowing the CCFL

regulator to turn on.