7

LT1786F

CCFL PGND (Pin 1): This pin is the emitter of an internal

NPN power switch. CCFL switch current flows through

this pin and permits internal, switch-current sensing. The

regulator provides a separate analog ground and power

ground to isolate high current ground paths from low

current signal paths. Linear Technology recommends the

use of star-ground layout techniques.

programming circuit. This pin internally regulates to

465mV. The pin accepts a DC input current signal of 0

µA

to 100

µA full scale from the DAC. This input signal is

converted to a 0

pin. As input programming current increases, the regu-

lated lamp current increases.

DIO (Pin 3): This pin is the common connection between

the cathode and anode of two internal diodes. The remain-

ing terminals of the two diodes connect to ground. In a

grounded-lamp configuration, DIO connects to the low

voltage side of the lamp. Bidirectional lamp current flows

in the DIO pin and thus the diodes conduct alternately on

half cycles. Lamp current is controlled by monitoring one-

half of the average lamp current. The diode conducting on

negative half cycles has one-tenth of its current diverted to

current provided by the lamp-current programmer circuit.

loop compensation and an averaging function to the half-

wave-rectified sinusoidal lamp current. Therefore, input

programming current relates to one-half of average lamp

current. This scheme reduces the number of loop com-

pensation components and permits faster loop transient

response in comparison to previously published circuits.

If a floating lamp configuration is used, ground the DIO

pin.

programmer circuit and the input of the current compara-

tor for the CCFL regulator. Its uses include frequency

compensation, lamp-current averaging for grounded-lamp

pin determines the current trip level for switch turn-off.

During normal operation this pin sits at a voltage between

0.95V (zero switch current) and 2.1V (maximum switch

current) with respect to analog ground (AGND). This pin

has a high impedance output and permits external voltage

clamping to adjust current limit. A single capacitor to

ground provides stable loop compensation. This simpli-

fied loop compensation method permits the CCFL regula-

tor to exhibit single-pole transient response behavior and

virtually eliminates transformer output overshoot.

CODE

0

64

1786 G27

16

32

48

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

DNL vs Code

CODE

0

64

1786 G28

16

32

48

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

INL vs Code