LT1786FCS datasheet(3/20 Pages) LINER

3 / 20 page

LT1786F

ELECTRICAL CHARACTERISTICS

TA = 25°C, VCC = SHUTDOWN = SMBSUS = SCL = SDA = 3.3V, BAT = Royer = BULB = 12V, ICCFL = CCFL VSW = Open,

DIO = IOUT = GND, CCFL VC = 0.5V, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

CCFL High-Side Sense Servo Current

BAT = 5V to 30V, ICCFL = 100µA,

0.1

0.16

%/V

Line Regulation

I(VC) = 0µA at CCFL VC = 1.5V

CCFL High-Side Sense Supply Current Current Measured into BAT and Royer Pins

100

150

µA

BULB Protect Servo Voltage

ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V,

6.5

7.0

7.5

Servo Voltage Measured between BAT and BULB Pins

BULB Input Bias Current

ICCFL = 100µA, I(VC) = 0µA at CCFL VC = 1.5V

µA

ILIM

CCFL Switch Current Limit

Duty Cycle = 50%

1.25

1.9

3.0

Duty Cycle = 75% (Note 3)

0.9

1.6

2.6

VSAT

CCFL Switch On Resistance

CCFL ISW = 1A

0.6

1.0

Ω

∆I

Supply Current Increase During

CCFL ISW = 1A

mA/A

∆ISW

CCFL Switch On Time

DAC Resolution

Bits

DAC Full-Scale Current

V(IOUT) = 0.465V

100

102

µA

100

104

µA

DAC Zero Scale Current

V(IOUT) = 0.465V

±200

DAC Differential Nonlinearity

±0.1

±1

LSB

DAC Supply Voltage Rejection

≤ VCC ≤ 6.5V, IOUT = Full Scale, V(IOUT) = 0.465V

0.2

LSB

IIN

Logic Input Current

≤ VIN ≤ VCC

±1

µA

VIH

High Level Input Voltage

ADR

VCC – 0.3

SMBSUS

2.4

SCL, SDA

1.4

VIL

Low Level Input Voltage

SMBSUS, ADR

0.8

SCL, SDA

0.6

VOL

Low Level Output Voltage

IOUT = 3mA, SDA Only

0.4

IOUT = 1.6mA, SMBSUS = 0V, Measured at SHDN Pin

0.4

SMBus Timing (Notes 4, 5)

fSMB

SMB Operating Frequency

100

kHz

tBUF

Bus Free Time Between Stop and Start Condition

4.7

µs

tHD:STA

Hold Time After (Repeated) Start Condition

4.0

µs

tSU:STA

Repeated Start Condition Setup Time

4.7

µs

tSU:STO

Stop Condition Setup Time

4.0

µs

tHD:DAT

Data Hold Time

300

tSU:DAT

Data Setup Time

250

tLOW

Clock Low Period

4.7

µs

tHIGH

Clock High Period

4.0

µs

Clock/Data Fall Time

300

Clock/Data Rise Time

1000

Note 3: For duty cycles (DC) between 50% and 80%, minimum

guaranteed switch current is given by ILIM = 1.4(1.393 – DC) for the

LT1786F due to internal slope compensation circuitry.

Note 4: Timings for all signals are referenced to VIH and VIL signals.

Note 5: These parameters are guaranteed by design and are not tested in

production. Refer to the Timing Diagrams for additional information.

The q denotes specifications which apply over the specified operating

temperature range.

Note 1: TJ is calculated from the ambient temperature TA and power

dissipation PD according to the following formula:

LT1786FCS: TJ = TA + (PD)(100°C/W)

Note 2: Does not include switch leakage.

LT1786FCS 数据表(PDF) 3 Page - Linear Technology

LT1786FCS 数据表(HTML) 3 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载