LTC1093CSW datasheet(9/32 Pages) LINER

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LTC1091/LTC1092

LTC1093/LTC1094

INPUT

SHIFT

SAMPLE-

AND-HOLD

10-BIT

CAPACITIVE

DAC

AVCC

ANALOG

INPUT MUX

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

DOUT

CLK

CONTROL

AND

TIMING

1091/2/3/4 BD

REF+

DGND

AGND

V–

REF–

COMP

OUTPUT

SHIFT

DIN

10-BIT

SAR

DVCC

(Pin numbers refer to LTC1094)

BLOCK DIAGRA

VREF (Pin 11)(LTC1093): Reference Input. The reference

input must be kept free of noise with respect to AGND.

REF +, REF – (Pins 13, 14 )(LTC1094): Reference Input.

The reference input must be kept free of noise with respect

to AGND.

DIN (Pin 12/Pin 15): Data Input. The A/D configuration

word is shifted into this input.

DOUT (Pin 13/Pin 16): Digital Data Output. The A/D con-

version result is shifted out of this output.

CS (Pin 14/Pin 17): Chip Select Input. A logic low on this

input enables the LTC1093/LTC1094.

PI FU CTIO S

CLK (Pin 15/Pin 18): Shift Clock. This clock synchronizes

the serial data transfer.

VCC (Pin 16)(LTC1093): Positive Supply. This supply

must be kept free of noise and ripple by bypassing directly

to the analog ground plane.

AVCC, DVCC (Pins 19, 20)(LTC1094): Positive Supply.

This supply must be kept free of noise and ripple by

bypassing directly to the analog ground plane. AVCC and

DVCC should be tied together on the LTC1094.

LTC1093CSW 数据表(PDF) 9 Page - Linear Technology

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