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LTC1093CSW 数据表(PDF) 19 Page - Linear Technology |
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LTC1093CSW 数据表(HTML) 19 Page - Linear Technology |
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19 / 32 page  19 LTC1091/LTC1092 LTC1093/LTC1094 S APPLICATI I FOR ATIO Interfacing to the Parallel Port of the Intel 8051 Family The Intel 8051 has been chosen to demonstrate the interface between the LTC1091 and parallel port micro- processors. Normally, the CS, SCLK and DIN signals would be generated on three port lines and the DOUT signal read on a 4th port line. This works very well. However, we will demonstrate here an interface with the DIN and DOUT of the LTC1091 tied together as described in section 4. This saves one wire. The 8051 first sends the start bit and MUX address to the LTC1091 over the data line connected to P1.2. Then P1.2 is reconfigured as an input (by writing to it a one) and the 8051 reads back the 10-bit A/D result over the same data line. 1091-4 AI17 LTC1091 CS CLK DOUT DIN ANALOG INPUTS P1.4 P1.3 P1.2 8051 MUX ADDRESS A/D RESULT B9 B8 B7 B6 B5 B4 B3 B2 DOUT from LTC1091 Stored in 8051 RAM MSB R2 B1 B0 0 0 0 0 0 0 LSB R3 LABEL MNEMONIC OPERAND COMMENTS MOV A, #FFH DIN Word for LTC1091 SETB P1.4 Make Sure CS Is High CLR P1.4 CS Goes Low MOV R4, #04 Load Counter LOOP 1 RLC A Rotate DIN Bit into Carry CLR P1.3 SCLK Goes Low MOV P1.2, C Output DIN Bit to LTC1091 SETB P1.3 SCLK Goes High DJNZ R4, LOOP 1 Next Bit MOV P1, #04 Bit 2 Becomes an Input CLR P1.3 SCLK Goes Low MOV R4, #09 Load Counter LOOP MOV C, P1.2 Read Data Bit into Carry RLC A Rotate Data Bit into Acc SETB P1.3 SCLK Goes High CLR P1.3 SCLK Goes Low DJNZ R4, LOOP Next Bit MOV R2, A Store MSBs in R2 MOV C, P1.2 Read Data Bit into Carry SETB P1.3 SCLK Goes High CLR P1.3 SCLK Goes Low CLR A Clear Acc RLC A Rotate Data Bit from Carry to Acc MOV C, P1.2 Read Data Bit into Carry RRC A Rotate Right into Acc RRC A Rotate Right into Acc MOV R3, A Store LSBs in R3 SETB P1.4 CS Goes High 1091/2/3/4 AI18 CLK START MSBF B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 8051 P1.2 RECONFIGURED AS AN INPUT AFTER THE 4TH RISING CLK AND BEFORE THE 4TH FALLING CLK 8051 P1.2 OUTPUTS DATA TO LTC1091 LTC1091 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK SGL/ DIFF ODD/ SIGN CS DATA (DIN/DOUT) 12 MSBF BIT LATCHED INTO LTC1091 3 4 LTC1091 SENDS A/D RESULT BACK TO 8051 P1.2 |
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