LTC1093CSW datasheet(23/32 Pages) LINER

23 / 32 page

LTC1091/LTC1092

LTC1093/LTC1094

APPLICATI

I FOR ATIO

Figure 10. Poor Op Amp Settling Can Cause A/D Errors

Figure 9. Adequate Settling of Op Amp Driving Analog Input

5mV/DIV

µs/DIV

1091-4 F09

5mV/DIV

µs/DIV

1091-4 F10

RC Input Filtering

It is possible to filter the inputs with an RC network as

shown in Figure 11. For large values of CF (e.g., 1µF), the

capacitive input switching currents are averaged into a net

DC current. Therefore, a filter should be chosen with a small

resistor and large capacitor to prevent DC drops across the

resistor. The magnitude of the DC current is approximately

IDC = (60pF)(VIN/tCYC) and is roughly proportional to VIN.

When running at the minimum cycle time of 32

µs, the input

current equals 9

µA at VIN = 5V. In this case, a filter resistor

of 50

Ω will cause 0.1LSB of full-scale error. If a larger filter

resistor must be used, errors can be eliminated by increas-

ing the cycle time as shown in the typical curve of Maximum

Filter Resistor vs Cycle Time.

Input Leakage Current

Input leakage currents can also create errors if the source

resistance gets too large. For instance, the maximum input

leakage specification of 1

µA (at 125°C) flowing through a

source resistance of 1k

Ω will cause a voltage drop of 1mV

or 0.2LSB. This error will be much reduced at lower

temperatures because leakage drops rapidly (see the

typical curve of Input Channel Leakage Current vs

Temperature).

4. Sample-and-Hold

Single-Ended Inputs

The LTC1091/LTC1093/LTC1094 provide a built-in sample-

and-hold (S&H) function for all signals acquired in the single-

ended mode. This sample-and-hold allows conversion of

rapidly varying signals (see typical curve of S&H Acquisition

Time vs Source Resistance). The input voltage is sampled

during the tSMPL time as shown in Figure 8. The sampling

interval begins as the bit preceding the MSBF bit is shifted in

and continues until the falling CLK edge after the MSBF bit is

received. On this falling edge, the S&H goes into hold mode

and the conversion begins.

Figure 11. RC Input Filtering

RFILTER

VIN

CFILTER

1091-4 F11

LTC1091

“+”

“–”

IDC

LTC1093CSW 数据表(PDF) 23 Page - Linear Technology

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