13

LTC1649

lated at 5V in shutdown, and can be used as a keep-alive

supply for external circuitry if desired. Note that any

current in shutdown, and subtracts from the current

available to drive the external MOSFETs if the load remains

connected while the LTC1649 is active.

External Clock Synchronization

The LTC1649 SHDN pin can double as an external clock

input for applications that require a synchronized clock or

a faster switching speed. The SHDN pin terminates the

internal sawtooth wave and resets the oscillator immedi-

ately when it goes low, but waits 50

µs before shutting

down the rest of the internal circuitry. A clock signal

applied directly to the SHDN pin will force the LTC1649

internal oscillator to lock to its frequency as long as the

external clock runs faster than the internal oscillator

frequency. The LTC1649 can be synchronized to frequen-

cies between 250kHz and about 350kHz.

Frequencies above 350kHz can cause erratic current limit

operation and are not recommended.

Setting the Output Voltage

The LTC1649 feedback loop senses the output voltage at

the FB pin. The loop regulates FB to 1.265V; to set the

output voltage, FB should be connected to the output node

through a resistor divider, set up so the voltage at FB is

1.265V when the output is at the desired voltage (see

Figure 8). The upper end of R1 should be connected to the

output voltage as close to the load as possible, to minimize

errors caused by resistance in the output leads. The

bottom of R2 should be connected to the high power

ground node, at the GND pin of the LTC1649.

R1 and R2 should be chosen so that:

R2

(1.265V)

R2

An easy way to simplify the math is to choose

R2 = 12.65k

Ω. This simplifies the equation to:

10k

Ω

+ 1.265V

A typical 2.5V output application might use R1 = 12.35k

Ω,

R2 = 12.65k

Ω. The nearest standard 1% values are

R1 = 12.4k

Ω, R2 = 12.7kΩ, which gives an output voltage

of 2.5001V—pretty close to 2.5V.

Note that using 1% resistors can cause as much as 1%

error in the output voltage in a typical LTC1649 applica-

tion—a significant fraction of the total output error. 0.1%

or 0.25% feedback resistors are recommended for appli-

cations which require the output voltage to be controlled

to better than 3%.

LTC1649

GND

FB

1659 F08

R1

R2

+

Figure 8. Resistor Divider at FB Pin

LAYOUT CONSIDERATIONS

Grounding

Proper grounding is critical for the LTC1649 to obtain

specified output regulation. Extremely high peak currents

(as high as several amps) can flow between the bypass

currents can generate significant voltage differences be-

tween two points that are nominally both “ground.” As a

general rule, power and signal grounds should be totally

separated on the layout, and should be brought together

at only one point, right at the LTC1649 GND pin. This helps

minimize internal ground disturbances in the LTC1649,

while preventing excessive current flow from disrupting

the operation of the circuits connected to GND. The high

power GND node should be as compact and low imped-

ance as possible, with the negative terminals of the input