7

LTC1649

MOSFET Gate Drive

The LTC1649 is designed to operate from supplies as low

as 2.7V while using standard 5V logic-level N-channel

external MOSFETs. This poses somewhat of a challenge—

from as little as 2.7V, the LTC1649 must provide a 0V to

5V signal to the lower MOSFET, Q2, while the upper

MOSFET, Q1, requires a gate drive signal that swings from

with two specialized circuits. An onboard charge pump

turn supplies 5V gate drive to Q2. This 5V supply is also

circuitry to interface to the boosted driver supplies.

Gate drive for the top N-channel MOSFET, Q1, is supplied

Conveniently, the switching node at the source of Q1 rises

external charge pump as shown in Figure 2. This circuit

when the switching node is low. As the top MOSFET turns

cycle (typical) means the switching node at the source of

Q1 will return to ground during at least 7% of each cycle,

ensuring that the charge pump will always provide ad-

equate gate drive to Q1.

Synchronous Operation

The LTC1649 uses a synchronous switching architecture,

with MOSFET Q2 taking the place of the diode in a classic

buck circuit (Figure 3). This improves efficiency by reduc-

ing the voltage drop and the resultant power dissipation

offsets the additional gate drive required by the second

MOSFET, allowing the LTC1649 to achieve efficiencies in

the mid-90% range for a wide range of load currents.

Another feature of the synchronous architecture is that

unlike a diode, Q2 can conduct current in either direction.

This allows the output of a typical LTC1649 circuit to sink

current as well as sourcing it while remaining in regula-

tion. The ability to sink current at the output allows the

LTC1649 to be used with reactive or other nonconventional

loads that may supply current to the regulator as well as

drawing current from it.

Figure 3b. Synchronous Buck Architecture

Figure 3a. Classical Buck Architecture

LTC1649

Q1

L1

Q2

G1

G2

1649 F02

+

10

µF

+

1

µF

Q1

D1

CONTROLLER

1649 F03a

Q1

CONTROLLER

Q2

1649 F03b